Young Hwan Kim

 

CAD & SoC Design Laboratory March 2007

 

 

CAD / Design Technology Area (Click here for detailed information)

 

*      Circuit analysis

*      Timing verification / modeling of latch-based IPs

*      Low-power design and power estimation

*      Design technology under deep submicron effects

*           Power integrity / Signal integrity

*           Delay calculation under crosstalk

*           Statistical design under process variation

*             Leakage estimation/optimization

*             Timing analysis

 

 

SoC Design Area (Click here for detailed information)

 

*       High-performance PDP (Plasma Display Panel) circuits

*       High-performance LCD (Liquid Crystal Display) circuits

*       Cryptographic hardware

*       VLSI for multimedia applications